Recent Publications

2011

· M. Palesi, R. Holsmark, S. Kumar, V. Catania. Application Specific Routing Algorithms for Low Power NoC Design, Book Chapter in Low-Power Networks on Chip Edited by Christina Salvano, Marcello Lajolo and Gianluca Palermo, pages 113-150, Springer 2011.

· M. Palesi, S. Kumar, R. Marculescu. Editorial of the Special Issue on Network on Chip Architectures and Design Methodologies, Elsevier Microprocessors and Microsystems Journal. Jan 2011.

2010

· Rickard Holsmark, Shashi Kumar, Maurizio Palesi, A Multi-level routing scheme and router architecture to support hierarchical Routing in large Networks on Chip, International Workshop on Highly Parallel Processing on Chip (HPPC 2010), Italy, Aug. 2010.

· M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. A Novel Mechanism to Guarantee In-Order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip, IEEE Euro Micro DSD 2010, Sept. 2010.

· S. Mubeen and S. Kumar. Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms, IEEE Euro Micro DSD 2010, Sept. 2010.

· M. Palesi, S. Kumar, V. Catania. Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(3), pp. 426-440, March 2010.

· M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip. 4th Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, held in conjunction with the: 5th International Conference on High Performance Embedded Architectures and Compilers, Pisa, Italy, January 24, 2010.

2009

· M. Palesi, R. Holsmark, S. Kumar, V. Catania. Application Specific Routing Algorithms for Networks on Chip. IEEE Transactions on Parallel and Distributed Systems, Vol. 20, No. 3, March 2009, pages 316-330.

· A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark and J. Duato. Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Transactions on on Very Large Scale Integration Systems, Volume 17, Number 3, March 2009, pages 356-369.

· R.Holsmark, M. Palesi, S. Kumar, A. Mejia, HiRA: A Methodology for deadlock free routing in Hierarchical Networks on Chip, 3^rd ACM/IEEE International Symposium on Networks-on-Chip, May 2009, San Deigo, California, USA.

· S. Mubeen and S. Kumar. On Source Routing for Mesh Topology Network on Chip, 9^th Swedish System on Chip Conference (SSoCC 09), May, Arid, Sweden.

· M. Palesi, S. Kumar, V. Catania. Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms. , Journal of IET Computers and Digital techniques, Vol. 3, No. 5, pp. 413-429, 2009.

· R. Tornero, S. Kumar, S. Mubeen and J. M. Orduna. Distance Constrained Mapping to Support NoC Platforms based on Source Routing, 3^rd Highly Parallel Processing on Chip (HPPC 09) workshop, August 2009, Delft, Netherland.

2008

· G. Longo, S. Signorino, M. Palesi, R. Holsmark, S. Kumar, and V. Catania, Bandwidth Aware Routine Algorithms for Network-on-Chip, HiPEAC Workshop on Interconnection Architectures-On Chip Multichip, Jan. 27, 2008, Göteborg, Sweden.

· M. Palesi, G. Longo, S. Signorino, R. Holsmark, S. Kumar, V. Catania, Design of bandwidth aware and congestion avoiding efficient routing algorithms for Network on Chip platforms, 2nd IEEE International Symposium on Networks on Chip (NoCS2008), New Castles University, U.K., April 2008.

· D. Frazetta, G. Dimartino, M. Palesi, S. Kumar, V. Catania, Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links, IEEE International Euro-micro Conference on Digital System Design (DSD 2008), Sept. 2008.

· R. Holsmark, M. Palesi, S. Kumar, Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions. Journal of Systems Architecture, 54/3-4 (2008) pp. 427-440

· T. Bengtsson, S. Kumar, R. Ubar, A. Jutman, Z. Peng, Test Methods for Crosstalk Induced Delay and Glitch Faults in NoC Interconnects implementing Asynchronous Communication Protocols, Journal of IET Computer and Digital Techniques, Vol2, Issue6, pages 445-460, Nov. 2008.

2007

· Rickard.Holsmark and Shashi Kumar, Corrections to Chen and Chiu’s Fault Tolerant Routing Algorithm for Mesh Networks, Journal of Information Science and Engineering, Vol. 23, 1649-1662 (2007).

· M.Palesi, S.Kumar, R.Holsmark, V.Catania. Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. Proceeding of 14th Reconfigurable Architectures Workshop March 27-28, 2007, Long Beach, California, USA.

· Bertozzi, Davide; Kumar, Shashi; Palesi, Maurizio (Editors), Networks-on-Chip, Hindawi Publishing Corporation, 2007, ISBN 977-5945-90-9.

· Bertozzi, Davide; Kumar, Shashi; Palesi, Maurizio, Networks-on-Chip: Emerging Research Topics and Novel Ideas, Journal of VLSI, Hindawi publishers, Volume 2007, 2007.

2006

· Tomas Bengtsson, Shashi Kumar and Zebo Peng, Application Area Specific System Level Fault Models: A case study with a simple NoC Switch, International Design and Test Workshop (IDT 2006), Dubai, Nov. 19-20 Nov. 2006.

· Tomas Bengtsson, Shashi Kumar, Raimund Ubar and Artur Jutman, Off-line Testing of Crosstalk Induced Glitch Faults in NoC Interconnects, Proceedings of NORCHIP 2006, Linköping, Sweden,  221-226, Nov. 2006.

· Ruxandra Pop and Shashi Kumar, On performance Improvement of Concurrent Applications using Simultaneous Multithreaded Processors as NoC resources, Proceedings of NORCHIP 2006, Linköping, Sweden, Nov. 2006.

· M.Palesi, R.Holsmark, S.Kumar, V.Catania. A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems. International Conference on Hardware-Software Codesign and System Synthesis, Seoul, Korea, October 22-25, 2006.

· R.Holsmark, M.Palesi, S.Kumar. Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools. Croatia, Sept 2006.

· Tomas Bengtsson, Artur Jutman, Shashi Kumar, Zebo Peng, Raimund Ubar, Off-line Testing of Delay Faults in NoC Interconnects,, 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools. Croatia, Sept 2006.

· M.Palesi, S.Kumar, R.Holsmark. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. Proceedings of SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation. Samos, Greece, July 17-20, 2006.

· M.Palesi, R.Holsmark, S.Kumar, V.Catania. APSRA: A methodology for design of Application Specific Routing Algorithms for NoC Systems. Technical Report DIIT-TR-01-060406, Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Università di Catania, Italy, April 2006.

· R. Pop, S. Kumar, "Application Parallelism Exploitation using NoC with Multithreaded Processors”, Special Workshop on Future Interconnects and Network on Chip,10^th March, 2006, Munich, Germany. Abstract, Poster

· D. Andreasson, S. Kumar,”STAR: An Efficient Routing Strategy for NoC with Mixed QoS Requirements”, Special Workshop on Future Interconnects and Network on Chip,10^th March, 2006, Munich, Germany. Abstract, Poster

· T. Bengtsson, S. Kumar, , A. Jutman and R. Ubar, ”An Improved method for delay testing of asynchronous NoC interconnects”, Special Workshop on Future Interconnects and Network on Chip,10^th March, 2006, Munich, Germany.Abstract, Poster

· R. Holsmark, S.Kumar, “On options for accessing region in NoC”, Special Workshop on Future Interconnects and Network on Chip,10^th March, 2006, Munich, Germany. Abstract, Poster.

2005

· E. Hillung, R. Holsmark, S. Kumar, "Modeling and Evaluation of a Shared Memory Design for a Mesh Topology NoC Architecture", WMSCI '05, Orlando, USA, July 2005.

· R. Holsmark, S. Kumar,”Design Issues and Performance Evaluation of Mesh NoC with Regions”, in Proceedings of 23rd IEEE Norchip 2005, Oulu, Finland, November 2005

· T. Bengtsson, A. Jutman, S. Kumar R. Ubar, ”Delay testing of asynchronous NoC interconnects”, in Proceedings of 12th International Conference Mixed Design of Integrated Circuits and Systems (MixDes), June 2005.

· T. Bengtsson, A. Jutman, R. Ubar, S. Kumar, ” A method for crosstalk fault detection in o-chip buses”, in Proceedings of 23rd Norchip Conference, pp. 285-288, November 2005

· D. Andreasson and S. Kumar, “Slack-Time Aware Routing in NoC Systems”, Proceedings of International Symposium of Circuits and Systems, May 23-26, Kobe, Japan.

· D.Andreasson and S. Kumar, “Improving BE traffic QoS using GT slack in NoC Systems”, Proceedings of 23th IEEE Norchip Conference, 21 - 22 Nov 2005, Oulu, Finland.

· R.Pop and S. Kumar, “Mapping Applications to NoC Platforms with Multithreaded Processor Resources”, Proceedings of 23rd Norchip Conference, November 2005.

· R. Holsmark, S. Kumar, “Corrections to Chen and Chiu’s Fault Tolerant Routing Algorithm for Mesh Networks”, Under Review with Journal of Information Science and Engineering, Institute of Information Science, Academia Sinica, Taipei, Taiwan

2004

· Sushil Jain, Anshul Kumar and Shashi Kumar, Hybrid Multi-FPGA Board Evaluation by permitting limited multi-hop routing, Kluwer Journal of Design Automation of Embedded Systems, Vol. 8, pages 309-326, Kluwer Academic Publishers, 2004.

· M. Millberg, E. Nilsson, R. Thid, Shashi Kumar, and A. Jantsch. ”The Nostrum backbone - a communication protocol stack for networks on chip.”In Proceedings of the VLSI Design Conference, Mumbai, India, January 2004.

· Rickard Holsmark, Alf Johansson, Shashi Kumar, ”On connecting cores to packet switched on-chip networks: a case study with microblaze processor cores”, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, April 18-21, 2004, Slovakia.

· Bhavani Prasad Kommineni, Rajkumar Srinivasa, Rickard Holsmark, Alf Johansson, Shashi Kumar, “ Modeling and Evaluation of a NoC-Internet Interface”, Swedish System on Chip Conference, Båstad, April 13-14, 2004.

· Daniel Andreasson and Shashi Kumar,” On improving Best-Effort throughput by better utilization of Guaranteed-Throughput channels in an on-chip communication system”, Proceedings of the NORCHIP 2004 conference, Oslo Oct. 2004.

· Henrik Samuelsson and Shashi Kumar, “Ring Road Network on Chip architecture”, Proceedings of the NORCHIP 2004 conference, Oslo Oct. 2004.

· R. Holsmark, S. Kumar, Processor Evaluation Cube: A classification and survey of processor evaluation techniques, ISSN 1404 – 0018 Research Report 04:3, School of Engineering , Jönköping University, November 2004.

· R.Pop, S. Kumar, A Survey of Techniques for Mapping and Scheduling Applications to Network on Chip Systems, ISSN 1404 – 0018, Research Report 04:4, Scool of Engineering, Jönköping University, December 2004.

· T. Bengtsson, S. Kumar, A Survey of High Level Test Generation Methodologies and Fault Models, ISSN 1404 – 0018 Research Report 04:5, School of Engineering, Jönköping University, December 2004.

2003

· S. Kumar, On packet switched networks for on-chip communication, Book chapter in Networks on Chip, Editors A. Jantsch, H. Tenhunen, Kluwer Publishers, 2003.

· T. Lei, S. Kumar, “Algorithms and Tools for Networks on Chip based System Design”, SBCCI 2003, 16th Symposium on Integrated Circuits and Systems Design, Sao Paulo, Brazil, Sept 8-11, 2003.

· T. Lei, S. Kumar, “Optimizing Network on Chip Architecture Size for applications”, 5th International conference on ASIC, Beijing, China, Oct. 21-24, 2003.

· T. Lei, S. Kumar, “A two step genetic algorithm for mapping task graphs to a Network on Chip Architecture”, DSD 2003, Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, Turkey, Sept 1-6, 2003.

· R. Holsmark, M. Högberg, S. Kumar, “Modelling and Evaluation of a Network on Chip Architecture using SDL”, Proceedings of 11th International SDL Forum, Stuttgart, Germany, July 2003.